SLUS161F April 1999 – May 2020 UCC2813-0 , UCC2813-1 , UCC2813-2 , UCC2813-3 , UCC2813-4 , UCC2813-5 , UCC3813-0 , UCC3813-1 , UCC3813-2 , UCC3813-3 , UCC3813-4 , UCC3813-5
PRODUCTION DATA.
Refer to the PDF data sheet for device specific package drawings
The first step in compensating a fixed-frequency flyback is to verify if the converter operates in continuous conduction mode (CCM) or discontinuous conduction mode (DCM). If the primary inductance (L_{P}) is greater than the inductance for DCM-CCM boundary mode operation, called the critical inductance (L_{Pcrit}), then the converter operates in CCM. L_{Pcrit} is calculated with Equation 17.
For loads greater than 10% of P_{MAX} over the entire input voltage range, the selected primary inductance has value larger than the critical inductance. Therefore, the converter operates in CCM and the compensation loop requires design based on CCM flyback equations.
The current-to-voltage conversion is done externally with the ground-referenced current-sense resistor (R_{CS}) and the internal resistor divider sets up the internal current-sense gain, A_{CS} = 1.65. The IC technology allows tight control of the resistor-divider ratio, regardless of the actual resistor value variations.
The DC open-loop gain (G_{O}) of the fixed-frequency voltage control loop of a peak-current-mode control CCM flyback converter shown in Figure 33 is approximated by first using the output load (R_{OUT}), the primary to secondary turns ratio (N_{PS}), and the maximum duty cycle (D) as shown in Equation 18.
where
For this design, a converter with an output voltage (V_{OUT}) of 12 V, and 48 W relates to an output load (R_{OUT}) equal to 3 Ω at full load.
At minimum input bulk voltage of 75 V DC, the duty cycle reaches its maximum value of 0.615. The current sense resistance (R_{CS}) is 0.75 Ω and a primary to secondary turns-ratio (N_{PS}) is 10. The open-loop gain calculates to 14.95 dB.
A CCM flyback transfer function has two zeroes that are of interest. The ESR and the output capacitance contribute a left-half plane zero to the power stage, and the frequency of this zero (f_{ESRz}) is calculated with Equation 22.
The f_{ESRz} zero for a capacitance bank of three 680-µF capacitors (for a total output capacitance of 2040 µF) and a total ESR of 13 mΩ is located at 6 kHz.
CCM flyback converters have a zero in the right-half plane (RHP) of their transfer function. RHP zero has the same 20 dB/decade rising gain magnitude with increasing frequency just like a left-half plane zero, but it adds phase lag instead of lead. This phase lag tends to limit the overall loop bandwidth. The frequency location (f_{RHPz}) in Equation 23 is a function of the output load, the duty cycle, the primary inductance (L_{P}), and the primary to secondary side turns ratio (N_{PS}).
RHP zero frequency increases with higher input voltage and lighter load. Generally, the design requires consideration of the worst case of the lowest RHP zero frequency and the converter must be compensated at the minimum input and maximum load condition. With a primary inductance of 1.5 mH, at 75-V DC input, the RHP zero frequency (f_{RHPz}) is equal to 7.65 kHz at maximum duty cycle (full load).
The power stage has one dominant pole (ω_{P1}) which is in the region of interest, located at a lower frequency (f_{P1}) which is related to the duty cycle (D), the output load, and the output capacitance. There is also a double pole (f_{P2}) located at half the switching frequency of the converter. These poles are frequencies calculated with Equation 24 and Equation 25.
Subharmonic oscillation is the large signal instability that can occur in CCM flyback converters when duty cycles extend beyond 50%. The subharmonic oscillation increases the output voltage ripple and sometimes it even limits the power handling capability of the converter. Slope compensation to the CS signal is a technique used to eliminate the instability.
Ideally, the target of slope compensation is to achieve quality coefficient (Q_{P} = 1) at half of the switching frequency. The Q_{P} is calculated by Equation 26.
where
where
The optimal goal of the slope compensation is to achieve Q_{P} equal to 1, which means M_{C} must be 2.128 when D reaches it maximum value of 0.615.
The inductance current slope at the CS pin is calculated by Equation 28.
The compensation slope is calculated by Equation 29.
The compensation slope is added into the system through R_{RAMP} and R_{CSF}. A series capacitor (C_{RAMP}) is selected to approximate a high-frequency short circuit. Choose C_{RAMP} as 10 nF as the starting point, and make adjustments if required. R_{RAMP} and R_{CSF} form a voltage divider to scale the RC pin ramp voltage and inject the slope compensation into CS pin. Choose R_{RAMP} much larger than the R_{T} resistor so that it does not affect the frequency setting very much. In this design, R_{RAMP} is selected as 24.9 kΩ. The RC pin ramp slope is calculated with Equation 30.
To achieve 46.3 mV/µs compensation slope, R_{CSF} resistor is calculated with Equation 31.
The power stage open-loop gain and phase can be plotted as a function of frequency. The total open-loop transfer function, as a function of frequency, can be characterized by Equation 32.
where
The open-loop gain and phase Bode plots are graphed accordingly (see Figure 34 and Figure 35).