Question

A student has to use an appropriate number of:
A) NAND gates (only) to get the output \[{Y_1}\]
B) NOR gates (only) to get the output ${Y_2}$
From the given inputs A and B as shown in the diagram, identify the equivalent gate needed in each case. Show how one can connect an appropriate number of (i) NAND (ii) NOR gates respectively in the two cases to get these equivalent gates.

Answer 1

Hint: Think of the Boolean algebra that will result when you combine the gates in specific order to get precise outputs. Use more than one gate in the combination to get desired results.

Complete step by step solution:
The corresponding gates in the given two cases will be OR and the AND gate separately. The explanation of the same is given in the points below.
A) The combination of three NAND gates would form an OR gate as depicted in the diagram given below:

An OR gate is a digital logic gate with two or more inputs and a logical disconnect output. When one or more of its inputs is real, the result of an OR gate is true. If all the inputs of an OR gate are inaccurate, so the OR gate output is incorrect. There are two or three inputs and one output signal in an OR gate. It is called an OR door and only if any or all input signals are high is the output signal. The OR gate maps the input and output signals logically. The signal can be transferred and halted.

B) The combination of three NOR gates would give an AND gate, as given in the figure below,

An AND gate is a logical gate with a single output and two or more inputs. Logical multiplication laws are extended to an AND door. If all of the inputs are low, the output is also low at this gate. If all the inputs are high, the performance is high, too. An AND door may have many inputs, but the most common are 2 inputs and 3 AND gates.

Note: Try to make combinations of more than two similar gates while making a particular expression. Also pay attention to the Boolean algebra so formed due to the combination of the gates and remember that the NAND gate is a logic gate which gives a false output when all the inputs provided are true. Basically, its output is the complement of the output of AND gate logic.